This invention relates generally to fault detection in the manufacture of integrated circuits and more specifically to a versatile reconfigurable matrix based processor used for built-in self-testing of circuits.
Once manufactured, it is necessary to test very large scale integrated (VLSI) circuits to detect processing faults which could impair or inhibit correct operation of the circuit. Typically, this has been done by the external application of various test stimuli to inputs of the circuit and checking the actual response with an expected response.
As the complexity of some circuits increase, it is increasingly difficult to thoroughly test such circuits using just the external application of test stimuli. To facilitate testing of these more complex circuits, built-in self-test (BIST) circuitry is often included within the manufactured circuit to serve as an aid in the testing process. See for example, Edward J. McCluskey, Built-In Self-Test Techniques, IEEE Design & Test, Volume 2, Number 2, April 1985, pages 21-28. See also, Edward J. McCluskey, Built-In Self-Test Structures, IEEE Design & Test, Volume 2, Number 2, April 1985, pages 29-36.
In the prior art, one or more shift registers (called a scan path or scan chain) are used to generate input for the testing. Generally a hard-wired controller is used to generate the necessary control signals for the scan chain.
One disadvantage to the above-described prior systems is that a different hard-wired controller generally needs to be re-designed every time a different design configuration is generated. The process of re-designing a hard-wired controller during each fault grading process requires significant engineering development time and CPU time.